DEC "Firefly" prototype dual processor card developed by people who had worked on the "Dragon" at Xerox PARC

From DigiBarn Curator Bruce Damer: this artifact interested us as it carries some of the design concepts of the long lost last of the D* machines at PARC.

Words on this artifact from its contributor, Ed Satterthwaite, who worked at Xerox PARC in the 70s and 80s:

The Firefly was done at DEC by some people who had worked on Dragon at Xerox PARC, and some of the ideas about multiprocessor and memory systems were carried over.

Pictured below is a prototype of the second-generation Firefly dual-processor card following by the full history by Ed Satterthwaite.

Firefly

Image42.jpg

More background from Ed Satterthwaite

On the Xerox Dragon

During the early 1980's, PARC's Computer Science Laboratory began to develop VLSI design expertise and tools. One goal was to produce the Dragon, an intended successor to the Dorado that would implement the D* architecture in a VLSI chip set. In addition, the Dragon design supported memory that could be shared coherently among multiple processors using snooping caches and an appropriate bus protocol.

Increasing tensions between CSL management and the rest of Xerox during this same period resulted in a loss of part of the early design team in late 1983. Some of the same people subsequently jointed DEC's System Research Center and produced the Firefly, a multiprocessor workstation that used similar ideas about coherent shared memory but did not continue the Mesa instruction set.

Meanwhile, the Dragon effort continued at PARC. Working silicon was produced, but a small design team could not compete with the commercial microprocessor-based workstations that had become available by then. Work on the Dragon was abandoned without producing complete systems. The Dorados continued in use for several years, but they were gradually replaced by Sun workstations. Much of the Mesa/Cedar code base was initially ported by modifying the compilers to produce C code instead of Mesa byte codes. Aside from some loss of symbolic debugging information, that approach was largely successful.

Apparently, not much information on the Dragon was published. The most accessible description seems to be a 1987 paper by Atkinson and McCrieght, but it is fairly brief and is mostly a progress report.

The Dragon CPU implemented a PrincOps-like architecture with some extensions to increase execution efficiency. Most notably, register windows were added to support fast procedure call. To help the compilers do better on common subexpressions, some of the arithmetic instructions also acquired register-to-register-like variants for reaching into the evaluation stack without consuming their operands.

The initial Dragon implementation was a two-chip set. One chip was an IFU that fetched and decoded instructions into sequences of RISC-like operations. The companion EU chip held the register file and executed those instructions. A third chip would have been required for hardware support of floating point.

At the time of the Atkinson and McCreight paper, first pass silicon had been fabricated but did not run at design speed because of an error in the clock distribution. It's not clear whether the planned second pass silicon was ever produced in any quantity. Had the silicon run at design speed, simulations indicated that each Dragon processor would have had 2 to 3 times the performance of a Dorado.

On the History of the Firefly as related to the Dragon

During the early 1980's, PARC's Computer Science Laboratory began to develop VLSI design expertise and tools. One goal was to produce the Dragon, an intended successor to the Dorado that would implement the D* architecture in a VLSI chip set. Among other things, the Dragon design supported memory that could be shared coherently among multiple processors using snooping caches and an appropriate bus protocol.

As told in the books "Fumbling the Future" (Smith and Alexander, 1988) and "Dealers of Lightning" (Hiltzik, 1999), there was growing tension between CSL management and the rest of Xerox during this same period.

In late 1983, many senior people resigned and subsequently became the nucleus of DEC's System Research Center (SRC) in Palo Alto. SRC chose to pursue some of the shared memory ideas developed for the Dragon in a project that produced the Firefly workstation. In that sense, the Firefly might be considered part of the D* lineage. To produce working hardware quickly, however, the Firefly used off-the-shelf parts where possible. Initially, the DEC MicroVAX II was used for the CPUs. SRC built a CPU plus I/O board, a dual CPU board, memory boards and a series of display controllers, all of which fit into Digital packaging and used standard peripherals.

The Firefly was designed to accomodate up to 8 CPUs plus the i/o processor, but most systems used either 2 or 4. As a workstation, the Firefly was a mixed success. Existing software was not designed to exploit multiprocessors effectively, but some applications eventually did achieve impressive speedups. Many Fireflies were replaced by the MIPS-based DECStation 3100s and 5000s as the latter became available, but some remained in service for almost a decade, primarily as servers and gateways.

The initial Firefly dual CPU board was redesigned to use the CVAX, the first CMOS MicroVAX, when it appeared. The photos show a prototype of the CVAX-based board; the final version used surface-mount parts more extensively. This board was my first significant hardware project and
was done with a lot help from Chuck Thacker and Larry Stewart. A few hundred copies were produced.

In the photos, the larger chips with the circular heat sinks are the CVAX CPUs; the slightly smaller companion chips are the floating-point units. The two CPU and cache subsystems were largely independent and arranged as mirror images in the layout, but they shared an interface to the memory bus that was attached to the blue connectors at the front of the board.

Bibliographic References

R. A. Atkinson and E. M. McCreight, "The Dragon Processor," Proceedings of the Second International Conference on Architectural Support for Programming Languages (ASPLOS II), ACM Sigplan Notices, October 1987, 65-69.

C. P. Thacker and L. C. Stewart, "Firefly: a Multiprocessor Workstation," Proceedings of the Second International Conference on Architectural Support for Programming Languages (ASPLOS II), ACM Sigplan Notices, October 1987, 164-172.

C. P. Thacker, L. C. Stewart and E. H. Satterthwaite, "Firefly: a Multiprocessor Workstation," IEEE Transactions on Computers, 37(8), August 1988, 909-920.

Know anything more about this history? Get in touch!

See Also:

Bill Jackson's Digibarn Radio piece which explains how the DEC Firefly/Dragon came about as well as a lot of history of Xerox and Xerox PARC.

The DigiBarn's rendition of the original "Wildflower" site documenting the D* machines. and our pages on the Dandelion (Xerox Star 8010).